The present invention relates generally to voltage comparator circuits in integrated circuits and, more particularly, to a voltage comparator apparatus and method having improved kickback and jitter characteristics.
Comparators are widely used in integrated circuits that include, for example, analog-to-digital converters and voltage signal receivers on interconnections and clock distribution lines. A voltage comparator circuit provides an indication of which of two input voltages is larger or smaller. Since a voltage comparator often senses small differences between the input voltages and generates a digital output, a large amplification may be needed. The large amplification necessary for sensing small differences may be constructed using a differential amplifier operating in a non-linear region. The differential amplifier has two transistors connected as a source-coupled pair with one of the transistors turned off and the other transistor turned on. Therefore, the amplifier has one transistor turned on even under a static condition when the transistors are in a stable non-switching state.
As amplification circuits, comparators are susceptible to influence of noise on the input voltages. The noise on the input voltages causes erratic switching and false triggering of the comparator output. Thus, positive feedback can be applied to decrease the decision time limiting the effects of the noise on the inputs.
In one type of conventional CMOS voltage comparator, cross-coupled inverters are used to latch the state of a pair of input voltages applied to opposing legs of the latch. During a reset phase of the comparator, both the output voltage nodes are biased through control switching to a stable state (e.g., at the supply voltage), and are also isolated from the ground terminal of the device so as to prevent static power dissipation. When the input voltages are to be compared during the compare phase, a strobe (clock) signal deactivates the bias control circuitry, and couples the inverters/output nodes to the input voltages. The input voltage having the higher value will cause the transistor associated therewith to conduct more strongly, thus pulling the corresponding output node down more quickly, and in turn latching the output voltages to the complementary rail values.
However, one disadvantage associated with CMOS comparators that have their inputs active during the compare phase is coupling of the output voltages to the input nodes. In particular, the kickback caused by the output voltage nodes when transitioning from the metastable state can in turn cause jitter on the input voltages. Unfortunately, when attempting to amplify a small input voltage differential, it is possible that the resulting jitter on the input signals can actually cause the comparator to latch the incorrect state. As result, the overall performance of the comparator is diminished, in terms of resolution (i.e., the accuracy of the comparator, in bits, given a regeneration time) and in terms of offset (i.e., the magnitude of applied input voltage differential, below which results in an indeterminate output decision).
Accordingly, it would be desirable to be able to provide a voltage comparator with improved immunity to output kickback and jitter on the input voltage signals.